1. Field of the Invention
The present invention relates to a multiprocessor system and, more particularly, to a computer system having interrupt controllers in units of processor modules.
2. Description of the Related Art
In a conventional multiprocessor system, a first method of causing an I/O interface to supply an interrupt signal to a processor is known as a method of causing an input/output (I/O) interface (device) to interrupt a processor. According to this method, the input/output (I/O) interface designates one processor, and the interrupt signal is supplied to the designated processor.
According to the second method, processors are connected to I/O interfaces with special hardware (communication circuit or the like), and each of the I/O interfaces can supply an interrupt signal to only a predetermined processor.
In either method, interrupt controllers and processors are arranged in a one-to-one correspondence. When each I/O interface generates an interrupt request, each interrupt controller outputs an interrupt signal to a corresponding processor.
However, according to the first method, when a processor designated by an I/O interface cannot receive the interrupt signal, the interrupt request from the I/O interface is set in a standby state, and processing is delayed. On the other hand, according to the second method, the processors are connected to the I/O interface through special hardware in advance. Therefore, interrupt control of the microprocessor is quite different from interrupt control of a single-microprocessor system. For this reason, single-processor software must be considerably changed to be used in a microprocessor.